View LY61L1288RL-15E_7404008.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ly61l1288 rev. 1.5 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 0 ? revision history revision description issue date rev. 1.0 initial issue jul.25.2004 rev. 1.1 delete icc1 spec. sep.21.2004 rev. 1.2 a dded i grade spec. revised test condition of i cc /i sb1 /i dr revised v term to v t1 and v t2 revised features & ordering information lead free and green package available to green package available deleted t solder in absolute maximun ratings added packing type in ordering information a pr.20.2009 rev. 1.3 a dding pkg type : 32 tsop-ii revised package outline dimension in page 8 jan.5.2010 rev. 1.4 rev. 1.5 revised package outline dimension in page 8 revised ordering information in page 10 ma y .7.2010 aug.25.2010
ly61l1288 rev. 1.5 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 1 ? features ? fast access time : 8/10/12/15ns ? low power consumption: operating current : 80/75/70/65ma (typ.) standby current : 0.6ma (typ.) ? single 3.3v power supply ? all inputs and outputs ttl compatible ? fully static operation ? tri-state output ? data retention voltage : 2.0v (min.) ? green package available ? package : 32-pin 8mm x 13.4mm stsop 32-pin 400 mil tsop-ii general description the ly61l1288 is a 1,048,576-bit high speed cmos static random ac cess memory organized as 131,072 words by 8 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the ly61l1288 is well designed for high speed system application. easy expansion is provided by using an active low chip enable(ce#). the active low write enable(we#) controls both writing and reading of the memory. the ly61l1288 operates from a single power supply of 3.3v and all inputs and outputs are fully ttl compatible product family product family operating temperature vcc range speed power dissipation standby(i sb1, typ.) operating(icc,typ.) ly61l1288 0 ~ 70 3.15 ~ 3.6v 8/10ns 0.6ma 80/75ma ly61l1288 0 ~ 70 3.0 ~ 3.6v 12/15ns 0.6ma 70/65ma ly61l1288(e) -20 ~ 80 3.15 ~ 3.6v 8/10ns 0.6ma 80/75ma ly61l1288(e) -20 ~ 80 3.0 ~ 3.6v 12/15ns 0.6ma 70/65ma ly61l1288(i) -40 ~ 85 3.15 ~ 3.6v 8/10ns 0.6ma 80/75ma ly61l1288(i) -40 ~ 85 3.0 ~ 3.6v 12/15ns 0.6ma 70/65ma functional block diagram decoder i/o data circuit control circuit 128kx8 memory array column i/o a0-a16 vcc vss dq0-dq7 ce# we# oe# pin description symbol description a0 - a16 address inputs dq0 ? dq7 data inputs/outputs ce# chip enable input we# write enable input oe# output enable input v cc power supply v ss ground
ly61l1288 rev. 1.5 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 2 ? pin configuration stsop vss a0 a1 a2 a3 dq5 a15 dq3 we# a4 a5 a6 vcc a13 oe# dq7 dq6 vcc dq4 a12 a11 a10 a9 a7 a8 ly61l1288 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 a16 ce# a14 dq0 dq1 dq2 vss 32 31 29 30 ly61l1288 a2 a1 a0 oe# ce# dq0 dq1 vcc vss a8 a4 dq7 dq6 dq5 vss vcc dq4 tsop-ii 21 10 9 8 7 6 5 4 3 2 1 12 11 15 14 16 17 18 19 20 a5 a3 dq3 we# a16 a15 a11 dq2 a6 a7 a10 a12 25 22 23 24 32 29 30 31 26 27 28 a9 a13 a14 13
ly61l1288 rev. 1.5 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 3 ? absolute maximun ratings* parameter symbol rating unit voltage on v cc relative to v ss v t1 -0.5 to 4.6 v voltage on any other pin relative to v ss v t2 -0.5 to v cc +0.5 v operating temperature t a 0 to 70(c grade) -20 to 80(e grade) -40 to 85(i grade) storage temperature t stg -65 to 150 power dissipation p d 1 w dc output current i out 50 ma *stresses greater than those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliabil ity. truth table mode ce# oe# we# i/o operation supply current standby h x x high-z i sb ,i sb1 output disable l h h high-z i cc read l l h d out i cc write l x l d in i cc note: h = v ih , l = v il , x = don't care. dc electrical characteristics parameter symbol test condition min. typ. * 4 max. unit supply voltage v cc -8/-10 3.15 3.3 3.6 v -12/-15 3.0 3.3 3.6 v input high voltage v ih *1 2.0 - v cc +0.5 v input low voltage v il *2 - 0.3 - 0.8 v input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage current i lo v cc R v out R v ss , output disabled - 1 - 1 a output high voltage v oh i oh = -4m a 2.4 - - v output low voltage v ol i ol = 8m a - - 0.4 v average operating power supply current i cc cycle time = min. ce# = v il , i i/o = 0ma other pins at v ih or v il -8 - 80 150 m a -10 - 75 120 m a -12 - 70 100 m a -15 - 65 90 m a standby power supply current i sb ce# = v ih, others at v ih or v il -3 10 m a i sb1 ce# v R cc -0.2v, other pins at 0.2v or v cc -0.2v - 0.6 3 *5 ma notes: 1. v ih (max) = v cc + 3.0v for pulse width less than 10ns. 2. v il (min) = v ss - 3.0v for pulse width less than 10ns. 3. over/undershoot specifications are characterized, not 100% tested. 4. typical values are included for reference only and are not guaranteed or tested. typical valued are measured at v cc = v cc (typ.) and t a = 25 5. 1ma for special request
ly61l1288 rev. 1.5 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 4 ? capacitance (t a = 25 , f = 1.0mhz) parameter symbol min. ma x unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by devic e characterization, but not production tested. ac test conditions input pulse levels 0.2v to v cc -0.2v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l = 30pf + 1ttl, i oh / i ol = -4ma/8m a ac electrical characteristics (1) read cycle parameter sym. ly61l1288 -8 ly61l1288 -10 ly61l1288 -12 ly61l1288 -15 unit min. max. min. max. min. max. min. max. read cycle time t rc 8 - 10 - 12 - 15 - ns a ddress access time t aa - 8 - 10 - 12 - 15 ns chip enable access time t ace - 8 - 10 - 12 - 15 ns output enable access time t oe -4-5-6 - 7 ns chip enable to output in low-z t clz * 2-2-3- 4 - ns output enable to output in low-z t olz * 0-0-0- 0 - ns chip disable to output in high-z t chz * -4-5-6 - 7 ns output disable to output in high-z t ohz * -4-5-6 - 7 ns output hold from address change t oh 3-3-3- 3 - ns (2) write cycle parameter sym. ly61l1288 -8 ly61l1288 -10 ly61l1288 -12 ly61l1288 -15 unit min. max. min. max. min. max. min. max. write cycle time t wc 8 - 10 - 12 - 15 - ns a ddress valid to end of write t aw 6.5 - 8 - 10 - 12 - ns chip enable to end of write t cw 6.5 - 8 - 10 - 12 - ns a ddress set-up time t as 0-0-0- 0 - ns write pulse width t wp 6.5 - 8 - 9 - 10 - ns write recovery time t wr 0-0-0- 0 - ns data to write time overlap t dw 5-6-7- 8 - ns data hold from end of write time t dh 0-0-0- 0 - ns output active from end of write t ow * 1.5 - 2 - 3 - 4 - ns write to output in high-z t whz * -5-6-7 - 8 ns *these parameters are guaranteed by device characterization, but not production tested.
ly61l1288 rev. 1.5 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 5 ? timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc previous data valid read cycle 2 (ce# and oe# controlled) (1,3,4,5) dout data valid t oh oe# t ace ce# t aa address t rc high-z high-z t clz t olz t oe t chz t ohz notes : 1.we# is high for read cycle. 2.device is continuously selected oe# = low, ce# = low . 3.address must be valid prior to or coincident with ce# = low , ; otherwise t aa is the limiting parameter. 4.t clz , t olz , t chz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz.
ly61l1288 rev. 1.5 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 6 ? write cycle 1 (we# controlled) (1,2,3,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc (4) t ow write cycle 2 (ce# controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc notes : 1.we#, ce# must be high during all address transitions. 2.a write occurs during the overlap of a low ce#, low we#. 3.during a we# controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the out put state, and input signals must not be applied. 5.if the ce# low transition occurs simultaneously with or after we# low transition, the outputs remain in a high impedance stat e. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state.
ly61l1288 rev. 1.5 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 7 ? data retention characteristics parameter symbol test cond ition min. typ. max. unit v cc for data retention v dr ce# v R cc - 0.2v 2.0 - 3.6 v data retention current i dr v cc = 2.0v ce# v R cc - 0.2v others at 0.2v or v cc - 0.2v - 0.4 2 ma chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform vcc ce# v dr R 2.0v ce# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.)
ly61l1288 rev. 1.5 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 8 ? package outline dimension 32 pin 8mm x 13.4mm stsop package outline dimension 1 16 17 32 c l hd d "a" e e 12 (2x) 12 (2x) seating plane y 32 17 16 1 c a2 a1 l a 0.254 0 gauge plane 12 (2x) 12 (2x) seating plane "a" datail view l1 b unit sym. inch(base) mm(ref) a 0.049 (max) 1.25 (max) a1 0.004 0.002 0.10 0.05 a2 0.039 0.002 1.00 0.05 b 0.009 0.002 0.22 0.05 c 0.006 0.002 0.155 0.055 d 0.465 0.008 11.80 0.20 e 0.315 0.008 8.00 0.20 e 0.020 (typ) 0.50 (typ) hd 0.528 0.008 13.40 0.20. l 0.02 0.008 0.50 0.20 l1 0.031 0.005 0.8 0.125 y 0.003 (max) 0.076 (max) 0 o 5 o 0 o 5 o
ly61l1288 rev. 1.5 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 9 ? 32-pin 400mil tsop- package outline dimension
ly61l1288 rev. 1.5 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 10 ? ordering information
ly61l1288 rev. 1.5 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 11 ? this page is left blank intentionally.

▲Up To Search▲

Price & Availability of LY61L1288RL-15E

	To Download LY61L1288RL-15E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .